sem tempo - parte final

Arquitetura de Computadores

Consider three processors with different cache configurations:

Cache 1: Direct-mapped with one-word blocks
Cache 2: Direct-mapped with four-word blocks
Cache 3: Two-way set associative with four-word blocks

The following miss rate measurements have been made:

Cache 1: Instruction miss rate is 4%; data miss rate is 6%.
Cache 2: Instruction miss rate is 2%; data miss rate is 4%.
Cache 3: Instruction miss rate is 2%; data miss rate is 3%.

For these processors, one-half of the instructions contain a data reference. Assume that the cache miss penalty is 6 + Block size in words. The CPI for this workload was measured on a processor with cache 1 and was found to be 2.0. Determine which processor spend the most cycles on cache misses.

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Banco de Dados

A database used in an order-entry system is to contain information about customers, items, and orders. The following information is to be included:

For each customer:
- Customer number (unique)
- "Ship-to" addresses (several per customer)
- Balance
- Credit limit
- Discount

For each order:
- Heading information:
-- Customer number
-- Ship-to address
-- Date of order
- Detail lines (several per order):
-- Item number
-- Quantity ordered

For each item:
- Item number (unique)
- Manufacturing plants
- Quantity on hand at each plant
- Stock danger level for each plant
- Item description

For intemal processing reasons, a "quantity outstanding" value is associated with each detail line of each order: this value is initially set equal to the quantity of the item ordered and is progressively reduced to zero as partial shipments are made. Again, design a database for this data. As in the previous exercise, state any assumptions you make regarding dependencies.

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